"Top picks" for computer science research

Research work at CDNC was selected for Top Picks in Hardware and Embedded Security two years in a row!

The “top picks” in hardware security represent the top most impactful papers that have been published in the area in the last six years. Top pick papers span a gamut of topics in hardware, microarchitecture, and embedded security from leading conferences. They are selected from conference and journal papers that have appeared in leading hardware security conferences. Papers on the shortlist are invited to the “Top Picks” workshop, collocated with the International Conference on Computer-Aided Design (ICCAD). The authors are required to present the paper at the workshop, which is mandatory for consideration to be one of “Top Picks”.  Selected papers are then invited for submission to a "Top Picks" special issue of a renowned journal like IEEE Design and Test (D&T) or Transactions on Computer-Aided Design (TCAD).

Forschungsteam um Prof. Tahoori
Research Team: Jonas Krautter, Dennis Gnad, Prof. Dr. Mehdi Tahoori (f.l.t.r.).


Recently, a new type of computer chip, a so-called Field-Programmable Gate Array (FPGA), is increasingly used to accelerate various computing tasks, for instance those used for Artificial Intelligence (aka "Machine Learning") tasks. In the use case of FPGAs as accelerators in data centers, researchers at CDNC have found various new security flaws, with possible solutions proposed as well.

More about security flaws in FPGAs:

[1] F. Schellenberg, D. R. E. Gnad, A. Moradi, M. B. Tahoori, "An Inside Job: Remote Power Analysis Attacks on FPGAs", in Proceedings of Design, Automation & Test in Europe (DATE), 2018, Germany. (Top Picks in Hardware Security 2019)
[2] J. Krautter, D. R. E. Gnad, M. B. Tahoori, "FPGAhammer: Remote Voltage Fault Attacks on Shared FPGAs, suitable for DFA on AES", in IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), 2018. (Top Picks in Hardware Security 2020)
[3] J. Krautter, D. R. E. Gnad, M. B. Tahoori, "Mitigating Electrical-Level Attacks towards Secure Multi-Tenant FPGAs in the Cloud", in ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2019.
[4] J. Krautter, D. R. E. Gnad, F. Schellenberg, A. Moradi, and M. B. Tahoori, "Active Fences against Voltage-based Side Channels in Multi-Tenant FPGAs", in Proceedings of the International Conference on Computer-Aided Design (ICCAD), 2019, USA.